The invention relates to a semiconductor integrated circuit including a detection circuit for detecting a change of a first and/or a second digital input signal on a first and a second input terminal, respectively, the detection circuit delivering an output pulse signal having a predetermined duration in response to said change, the detection circuit comprising:
a first resettable delay circuit having an input terminal for receiving said first input signal and an output terminal for delivering a first output signal;
a second resettable delay circuit having an input terminal for receiving said second input signal and an output terminal for delivering a second output signal; and
a gate circuit having input terminals and an output terminal for delivering said output pulse signal on said output terminal.
A circuit of the type mentioned above is known from European Patent Application EP-A-0 232 038, the U.S. counterpart of which, U.S. Pat. No. 4,717,835, is incorporated herein by reference. Said circuit can e.g. be used in semiconductor memory devices for generating a pulse when an address change has been detected by the detection circuit, in order to promote discharge of word lines, charging bit lines, etcetera. Said pulse has a pulse width which is not shorter than a normal pulse width, even when noise appears on the address input signals.